Wafer level packaging provides a complete electronic device package at the wafer level. This provides a package having a high density of integrated circuits in a small or ultra-thin profile package. Electronic devices and associated software applications continue to demand more memory and processing power from chip packages. However, electronic devices that use such chip packages have continued to shrink. Thus, the demand for integrated circuit packages having a high density in a smaller package has also increased. While it is desirable to design a new die that meets all of the needs of the market, such a design may not be feasible or ready for market. Thus, dies or chips are connected together, e.g., stacked, to achieve the desired density and electronic capacity. Wafer level packaging is used to meet these demands. However, most wafer level packaging processes have not had industrial success as such processes require a significant amount of wafer thinning followed by etching or laser drilling processes to create through holes in the wafer level package.